/* SPDX-License-Identifier: (GPL-2.0)
 * This file is part of the CAN-CTRL IP Core driver for Linux
 *
 * Copyright (C) Fraunhofer-Institut for Photonic Microsystems (IPMS)
 * Maria-Reiche-Str. 2
 * 01109 Dresden
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * \file can_linux_registers.h
 * \author  This file was automatically generated by the HAL_gen.py script
 * \date   18/01/2024
 * \brief  Holds all necessary register definitions of the CAN_CTRL in struct form.
 *
 */

#ifndef CAN_LINUX_REGISTERS_H
#define CAN_LINUX_REGISTERS_H

#include "hal_porting.h"

/**
 * @brief CAN node configuration structure
 */
typedef union {
	struct {
		uint8_t CES: 1; /**< CAN Error Signaling: disabled (0) or enabled (1) */
		uint8_t ROP: 1; /**< Restricted OPeration: disabled (0) or enabled (1) */
		uint8_t TMSE: 1; /**< CAN XL Transceiver Mode Switch Enable: disabled (0) or enabled (1) */
		uint8_t: 5; /**< Reserved */
	};
	uint8_t VALUE;
} CAN_CTRL_NODECFG_t;

/**
 * @brief CiA 603 Time-Stamping Configuration structure
 */
typedef union {
	struct {
		uint8_t TSEN: 1; /**< Time-Stamping ENable: disabled (0) or enabled (1) */
		uint8_t TSPOS: 1; /**< Time-Stamping POSition: SOF (0) or EOF (1) */
		uint8_t: 6; /**< Reserved */
	};
	uint8_t VALUE;
} CAN_CTRL_TSCFG_t;

/**
 * @brief CAN bit timing: arbitration / classic CAN structure
 */
typedef union {
	struct {
		uint32_t AC_SEG_1: 9; /**< CAN bit timing: arbitration / classic CAN    segment 1 (start of bit to SP) */
		uint32_t: 7; /**< Reserved */
		uint32_t AC_SEG_2: 7; /**< CAN bit timing: arbitration / classic CAN    segment 2 (SP to end of bit) */
		uint32_t: 1; /**< Reserved */
		uint32_t AC_SJW: 7; /**< CAN bit timing: arbitration / classic CAN    Synchronization Jump Width */
		uint32_t: 1; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_AC_TIME_t;

/**
 * @brief CAN bit timing: CAN FD data bit rate structure
 */
typedef union {
	struct {
		uint32_t FD_SEG_1: 8; /**< CAN bit timing: CAN FD data bit rate         segment 1 (start of bit to SP) */
		uint32_t: 8; /**< Reserved */
		uint32_t FD_SEG_2: 7; /**< CAN bit timing: CAN FD data bit rate         segment 2 (SP to end of bit) */
		uint32_t: 1; /**< Reserved */
		uint32_t FD_SJW: 7; /**< CAN bit timing: CAN FD data bit rate         Synchronization Jump Width */
		uint32_t: 1; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_FD_TIME_t;

/**
 * @brief CAN bit timing: CAN XL data bit rate structure
 */
typedef union {
	struct {
		uint32_t XL_SEG_1: 8; /**< CAN bit timing: CAN XL data bit rate         segment 1 (start of bit to SP) */
		uint32_t: 8; /**< Reserved */
		uint32_t XL_SEG_2: 7; /**< CAN bit timing: CAN XL data bit rate         segment 2 (SP to end of bit) */
		uint32_t: 1; /**< Reserved */
		uint32_t XL_SJW: 7; /**< CAN bit timing: CAN XL data bit rate         Synchronization Jump Width */
		uint32_t: 1; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_XL_TIME_t;

/**
 * @brief CAN bit timing: (all)                        prescaler structure
 */
typedef union {
	struct {
		uint8_t PRESC: 5; /**< CAN bit timing: (all)                        prescaler */
		uint8_t: 3; /**< Reserved */
	};
	uint8_t VALUE;
} CAN_CTRL_PRESC_t;

/**
 * @brief rearbitration and retransmission limits structure
 */
typedef union {
	struct {
		uint8_t REALIM: 3; /**< Rearbitration Limit */
		uint8_t: 1; /**< Reserved */
		uint8_t RETLIM: 3; /**< Retransmission Limit */
		uint8_t: 1; /**< Reserved */
	};
	uint8_t VALUE;
} CAN_CTRL_RELIM_t;

/**
 * @brief INTerrupt Flag Register: no interrupt (0) or interrupt pending (1) structure
 */
typedef union {
	struct {
		uint32_t AIF: 1; /**< Abort Interrupt Flag */
		uint32_t EIF: 1; /**< Error Interrupt Flag */
		uint32_t TSIF: 1; /**< Transmission Secondary Interrupt Flag */
		uint32_t TPIF: 1; /**< Transmission Primary Interrupt Flag */
		uint32_t RAFIF: 1; /**< RB Almost Full Interrupt Flag */
		uint32_t RFIF: 1; /**< RB Full Interrupt Flag */
		uint32_t ROIF: 1; /**< RB Overflow Interrupt Flag */
		uint32_t RIF: 1; /**< Receive Interrupt Flag */
		uint32_t BEIF: 1; /**< Bus Error Interrupt Flag */
		uint32_t ALIF: 1; /**< Arbitration Lost Interrupt Flag */
		uint32_t EPIF: 1; /**< Error Passive Interrupt Flag */
		uint32_t TTIF: 1; /**< TTCAN: Time Trigger Interrupt Flag */
		uint32_t TEIF: 1; /**< TTCAN: Trigger Error Interrupt Flag */
		uint32_t WTIF: 1; /**< TTCAN: Watch Trigger Interrupt Flag */
		uint32_t MDWIF: 1; /**< Memory Protection (ECC): Data Warning Interrupt Flag */
		uint32_t MDEIF: 1; /**< Memory Protection (ECC): Data Error Interrupt Flag */
		uint32_t MAEIF: 1; /**< Memory Protection (ECC): Address Error Interrupt Flag */
		uint32_t SEIF: 1; /**< DMR / TMR: Safety Error Interrupt Flag */
		uint32_t SWIF: 1; /**< DMR / TMR: Safety warning interrupt flag */
		uint32_t: 11; /**< Reserved */
		uint32_t EPASS: 1; /**< Error Passive status */
		uint32_t EWARN: 1; /**< Error WARNing limit reached */
	};
	uint32_t VALUE;
} CAN_CTRL_INTF_t;

/**
 * @brief INTerrupt Enable Register: disabled (0) or enabled (1) structure
 */
typedef union {
	struct {
		uint32_t: 1; /**< Reserved */
		uint32_t EIE: 1; /**< Error Interrupt Enable */
		uint32_t TSIE: 1; /**< Transmission Secondary Interrupt Enable */
		uint32_t TPIE: 1; /**< Transmission Primary Interrupt Enable */
		uint32_t RAFIE: 1; /**< RB Almost Full Interrupt Enable */
		uint32_t RFIE: 1; /**< RB Full Interrupt Enable */
		uint32_t ROIE: 1; /**< RB Overflow Interrupt Enable */
		uint32_t RIE: 1; /**< Receive Interrupt Enable */
		uint32_t BEIE: 1; /**< Bus Error Interrupt Enable */
		uint32_t ALIE: 1; /**< Arbitration Lost Interrupt Enable */
		uint32_t EPIE: 1; /**< Error Passive Interrupt Enable */
		uint32_t TTIE: 1; /**< TTCAN: Time Trigger Interrupt Enable */
		uint32_t: 1; /**< Reserved */
		uint32_t WTIE: 1; /**< TTCAN: Watch Trigger Interrupt Enable */
		uint32_t MDWIE: 1; /**< Memory Protection (ECC): Data Warning Interrupt Enable */
		uint32_t: 3; /**< Reserved */
		uint32_t SWIE: 1; /**< DMR / TMR: Safety Warning Interrupt Enable */
		uint32_t: 13; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_INTE_t;

/**
 * @brief transmit status 1 structure
 */
typedef union {
	struct {
		uint16_t HANDLE: 8; /**< Handle for frame identification */
		uint16_t TSTAT: 3; /**< Transmission Status Code */
		uint16_t: 5; /**< Reserved */
	};
	uint16_t VALUE;
} CAN_CTRL_TSTAT_1_t;

/**
 * @brief transmit status 2 structure
 */
typedef union {
	struct {
		uint16_t HANDLE: 8; /**< Handle for frame identification */
		uint16_t TSTAT: 3; /**< Transmission Status Code */
		uint16_t: 5; /**< Reserved */
	};
	uint16_t VALUE;
} CAN_CTRL_TSTAT_2_t;

/**
 * @brief configuration and status structure
 */
typedef union {
	struct {
		uint8_t BUSOFF: 1; /**< Bus Off: error active / error passive (0) or bus off (1) */
		uint8_t: 4; /**< Reserved */
		uint8_t LBMI: 1; /**< Loop Back Mode, Internal: disabled (0) or enabled (1) */
		uint8_t LBME: 1; /**< Loop Back Mode, External: disabled (0) or enabled (1) */
		uint8_t RESET: 1; /**< software reset: no reset (0) or reset (1) */
	};
	uint8_t VALUE;
} CAN_CTRL_CFG_STAT_t;

/**
 * @brief transmit command structure
 */
typedef union {
	struct {
		uint8_t TSA: 1; /**< Transmit Secondary Abort: abort if (1) */
		uint8_t TSALL: 1; /**< Transmit Secondary ALL frames: start transmission if (1) */
		uint8_t TSONE: 1; /**< Transmit Secondary ONE frame: start transmission if (1) */
		uint8_t TPA: 1; /**< Transmit Primary Abort: abort if (1) */
		uint8_t TPE: 1; /**< Transmit Primary Enable: start transmission if (1) */
		uint8_t STBY: 1; /**< Transceiver Standby Mode: disabled (0) or enabled (1) */
		uint8_t LOM: 1; /**< Listen Only Mode: disabled (0) or enabled (1) */
		uint8_t TBSEL: 1; /**< Transmit Buffer SELect: PTB (0) or STB (1) */
	};
	uint8_t VALUE;
} CAN_CTRL_TCMD_t;

/**
 * @brief transmit control structure
 */
typedef union {
	struct {
		uint8_t TSSTAT: 2; /**< Transmit Secondary STATus */
		uint8_t TSFF: 1; /**< Transmit Secondary Full Flag */
		uint8_t: 1; /**< Reserved */
		uint8_t TTTBM: 1; /**< TTCAN: Transmit Buffer Mode */
		uint8_t TSMODE: 1; /**< Transmit Secondary MODE: FIFO (0) or priority reordering (1) */
		uint8_t TSNEXT: 1; /**< Transmit Secondary NEXT: select next STB slot if (1) */
		uint8_t FD_ISO: 1; /**< CAN FD ISO mode: Bosch CAN FD (0) or ISO 11898-1:2015 (1) */
	};
	uint8_t VALUE;
} CAN_CTRL_TCTRL_t;

/**
 * @brief receive control structure
 */
typedef union {
	struct {
		uint8_t RSTAT: 2; /**< Receive buffer STATus: empty (00), not almost full (01), almost full (10), full (11) */
		uint8_t: 1; /**< Reserved */
		uint8_t RBALL: 1; /**< Receive Buffer stores ALL data frames: only valid frames (0) or all (erroneous) frames (1) */
		uint8_t RREL: 1; /**< Receive buffer RELease: set RB slot as released if (1) */
		uint8_t ROV: 1; /**< Receive buffer OVerflow status: no overflow (0) or overflow(1) did occur */
		uint8_t ROM: 1; /**< Receive buffer Overflow Mode: overwrite oldest (0) or discard newest (1) frame */
		uint8_t SACK: 1; /**< Self-ACKnowledge: no self-ACK (0) or self-ACK if LBME=1 (1) */
	};
	uint8_t VALUE;
} CAN_CTRL_RCTRL_t;

/**
 * @brief warning limits structure
 */
typedef union {
	struct {
		uint8_t EWL: 4; /**< Error Warning Limit */
		uint8_t AFWL: 4; /**< receive buffer Almost Full Warning Limit */
	};
	uint8_t VALUE;
} CAN_CTRL_LIMIT_t;

/**
 * @brief Error and Arbitration Lost CAPture structure
 */
typedef union {
	struct {
		uint8_t ALC: 5; /**< Arbitration Lost Capture */
		uint8_t KOER: 3; /**< Kind Of ERror (error code) */
	};
	uint8_t VALUE;
} CAN_CTRL_EALCAP_t;

/**
 * @brief TTCAN: reference message structure
 */
typedef union {
	struct {
		uint32_t REF_ID: 29; /**< TTCAN: REFerence message IDentifier */
		uint32_t: 2; /**< Reserved */
		uint32_t REF_IDE: 1; /**< TTCAN: REFerence Message IDE bit */
	};
	uint32_t VALUE;
} CAN_CTRL_REF_MSG_t;

/**
 * @brief TTCAN: trigger configuration structure
 */
typedef union {
	struct {
		uint8_t TTPTR: 6; /**< TTCAN: Transmit Trigger TB slot Pointer */
		uint8_t: 2; /**< Reserved */
	};
	uint8_t VALUE;
} CAN_CTRL_TRIGCFG_0_t;

/**
 * @brief TTCAN: trigger configuration structure
 */
typedef union {
	struct {
		uint8_t TTYPE: 3; /**< TTCAN: Trigger Type */
		uint8_t: 1; /**< Reserved */
		uint8_t TEW: 4; /**< TTCAN: Transmit Enable Window */
	};
	uint8_t VALUE;
} CAN_CTRL_TRIGCFG_1_t;

/**
 * @brief TTCAN: TB slot management structure
 */
typedef union {
	struct {
		uint8_t TBPTR: 6; /**< TTCAN: TB slot pointer */
		uint8_t TBF: 1; /**< TTCAN: set TB slot to "filled" */
		uint8_t TBE: 1; /**< TTCAN: set TB slot to "empty" */
	};
	uint8_t VALUE;
} CAN_CTRL_TBSLOT_t;

/**
 * @brief TTCAN: configuration structure
 */
typedef union {
	struct {
		uint8_t TTEN: 1; /**< TTCAN: ENable */
		uint8_t T_PRESC: 2; /**< TTCAN: Timer PRESCaler */
		uint8_t: 5; /**< Reserved */
	};
	uint8_t VALUE;
} CAN_CTRL_TTCFG_t;

/**
 * @brief Safety Configuration structure
 */
typedef union {
	struct {
		uint8_t XMREN: 1; /**< DMR / TMR ENable: disabled (0) or enabled (1) */
		uint8_t XMRTE: 1; /**< DMR / TMR Test Enable */
		uint8_t XMRTP: 1; /**< DMR / TMR Test Pass */
		uint8_t: 5; /**< Reserved */
	};
	uint8_t VALUE;
} CAN_CTRL_FSCFG_t;

/**
 * @brief MEMory STATus structure
 */
typedef union {
	struct {
		uint8_t ACFA: 1; /**< ACF Accept: normal operation of AFC (0) or all frames accepted (1) */
		uint8_t TXS: 1; /**< Transmission Stop: normal operation (0) or transmission stopped (1) */
		uint8_t TXB: 1; /**< Transmission Block: normal operation (0) or transmission immediately blocked (1) */
		uint8_t HELOC: 2; /**< Host side memory Error LOCation: none (00), TBUF (01), RBUF (10), ACF (11) */
		uint8_t: 2; /**< Reserved */
		uint8_t MPEN: 1; /**< Memory Protection ENable: disabled (0) or enabled (1) */
	};
	uint8_t VALUE;
} CAN_CTRL_MEM_STAT_t;

/**
 * @brief MEMory Error Stimulation 0 structure
 */
typedef union {
	struct {
		uint8_t MEBP1: 6; /**< Memory Error: Bit Position 1 */
		uint8_t ME1EE: 1; /**< Memory Error: 1st Error Enable: disabled (0) or enabled (1) */
		uint8_t MEAEE: 1; /**< Memory Error: Address Error Enable: disabled (0) or enabled (1) */
	};
	uint8_t VALUE;
} CAN_CTRL_MEM_ES_0_t;

/**
 * @brief MEMory Error Stimulation 1 structure
 */
typedef union {
	struct {
		uint8_t MEBP2: 6; /**< Memory Error: Bit Position 2 */
		uint8_t ME2EE: 1; /**< Memory Error: 2nd Error Enable: disabled (0) or enabled (1) */
		uint8_t: 1; /**< Reserved */
	};
	uint8_t VALUE;
} CAN_CTRL_MEM_ES_1_t;

/**
 * @brief MEMory Error Stimulation 2 structure
 */
typedef union {
	struct {
		uint8_t MEEEC: 4; /**< Memory Error: Error Enable Counter */
		uint8_t MENEC: 4; /**< Memory Error: No Error Counter */
	};
	uint8_t VALUE;
} CAN_CTRL_MEM_ES_2_t;

/**
 * @brief MEMory Error Stimulation 3 structure
 */
typedef union {
	struct {
		uint8_t MEL: 2; /**< Memory Error Location: ACF (00), TBUF (01), RBUF (10), ACF (11) */
		uint8_t MES: 1; /**< Memory Error Side: host side (0) or CAN side (1) */
		uint8_t: 5; /**< Reserved */
	};
	uint8_t VALUE;
} CAN_CTRL_MEM_ES_3_t;

/**
 * @brief Acceptance Filter Control structure
 */
typedef union {
	struct {
		uint8_t ACFADR: 4; /**< Acceptance Filter Address */
		uint8_t: 4; /**< Reserved */
	};
	uint8_t VALUE;
} CAN_CTRL_ACFCTRL_t;

/**
 * @brief Acceptance filter enable, part 1 structure
 */
typedef union {
	struct {
		uint8_t AE_00: 1; /**< Acceptance filter #00 enable: disabled (0) or enabled (1) */
		uint8_t AE_01: 1; /**< Acceptance filter #01 enable: disabled (0) or enabled (1) */
		uint8_t AE_02: 1; /**< Acceptance filter #02 enable: disabled (0) or enabled (1) */
		uint8_t AE_03: 1; /**< Acceptance filter #03 enable: disabled (0) or enabled (1) */
		uint8_t AE_04: 1; /**< Acceptance filter #04 enable: disabled (0) or enabled (1) */
		uint8_t AE_05: 1; /**< Acceptance filter #05 enable: disabled (0) or enabled (1) */
		uint8_t AE_06: 1; /**< Acceptance filter #06 enable: disabled (0) or enabled (1) */
		uint8_t AE_07: 1; /**< Acceptance filter #07 enable: disabled (0) or enabled (1) */
	};
	uint8_t VALUE;
} CAN_CTRL_ACF_EN_0_t;

/**
 * @brief Acceptance filter enable, part 1 structure
 */
typedef union {
	struct {
		uint8_t AE_08: 1; /**< Acceptance filter #08 enable: disabled (0) or enabled (1) */
		uint8_t AE_09: 1; /**< Acceptance filter #09 enable: disabled (0) or enabled (1) */
		uint8_t AE_10: 1; /**< Acceptance filter #10 enable: disabled (0) or enabled (1) */
		uint8_t AE_11: 1; /**< Acceptance filter #11 enable: disabled (0) or enabled (1) */
		uint8_t AE_12: 1; /**< Acceptance filter #12 enable: disabled (0) or enabled (1) */
		uint8_t AE_13: 1; /**< Acceptance filter #13 enable: disabled (0) or enabled (1) */
		uint8_t AE_14: 1; /**< Acceptance filter #14 enable: disabled (0) or enabled (1) */
		uint8_t AE_15: 1; /**< Acceptance filter #15 enable: disabled (0) or enabled (1) */
	};
	uint8_t VALUE;
} CAN_CTRL_ACF_EN_1_t;

/**
 * @brief LLC frame: IDentifier structure
 */
typedef union {
	struct {
		uint32_t ID: 29; /**< LLC frame: IDentifier */
		uint32_t: 3; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_ACFC_IDENTIFIER_t;

/**
 * @brief LLC frame: format structure
 */
typedef union {
	struct {
		uint32_t DLC: 11; /**< LLC frame: Data Length Code */
		uint32_t: 5; /**< Reserved */
		uint32_t IDE: 1; /**< LLC frame: IDentifier Extension */
		uint32_t FDF: 1; /**< LLC frame: FD frame Format */
		uint32_t BRS: 1; /**< LLC frame: Bit Rate Switching */
		uint32_t XLF: 1; /**< LLC frame: XL frame Format */
		uint32_t RMF: 1; /**< LLC frame: Remote Frame */
		uint32_t SEC: 1; /**< LLC frame: Simple or Extended Content */
		uint32_t: 5; /**< Reserved */
		uint32_t LLC_ESI: 1; /**< LLC frame: Error State Indicator */
		uint32_t LBF: 1; /**< LLC frame: Loop-Back Frame */
		uint32_t: 3; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_ACFC_FORMAT_t;

/**
 * @brief LLC frame: type structure
 */
typedef union {
	struct {
		uint32_t SDT: 8; /**< LLC frame: Service Data Type */
		uint32_t VCID: 8; /**< LLC frame: Virtual CAN ID */
		uint32_t: 16; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_ACFC_TYPE_t;

/**
 * @brief LLC frame: IDentifier structure
 */
typedef union {
	struct {
		uint32_t ID: 29; /**< LLC frame: IDentifier */
		uint32_t: 3; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_ACFM_IDENTIFIER_t;

/**
 * @brief LLC frame: format structure
 */
typedef union {
	struct {
		uint32_t DLC: 11; /**< LLC frame: Data Length Code */
		uint32_t: 5; /**< Reserved */
		uint32_t IDE: 1; /**< LLC frame: IDentifier Extension */
		uint32_t FDF: 1; /**< LLC frame: FD frame Format */
		uint32_t BRS: 1; /**< LLC frame: Bit Rate Switching */
		uint32_t XLF: 1; /**< LLC frame: XL frame Format */
		uint32_t RMF: 1; /**< LLC frame: Remote Frame */
		uint32_t SEC: 1; /**< LLC frame: Simple or Extended Content */
		uint32_t: 5; /**< Reserved */
		uint32_t LLC_ESI: 1; /**< LLC frame: Error State Indicator */
		uint32_t LBF: 1; /**< LLC frame: Loop-Back Frame */
		uint32_t: 3; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_ACFM_FORMAT_t;

/**
 * @brief LLC frame: type structure
 */
typedef union {
	struct {
		uint32_t SDT: 8; /**< LLC frame: Service Data Type */
		uint32_t VCID: 8; /**< LLC frame: Virtual CAN ID */
		uint32_t: 16; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_ACFM_TYPE_t;

/**
 * @brief LLC frame: IDentifier structure
 */
typedef union {
	struct {
		uint32_t ID: 29; /**< LLC frame: IDentifier */
		uint32_t: 3; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_RBUF_IDENTIFIER_t;

/**
 * @brief LLC frame: format structure
 */
typedef union {
	struct {
		uint32_t DLC: 11; /**< LLC frame: Data Length Code */
		uint32_t: 5; /**< Reserved */
		uint32_t IDE: 1; /**< LLC frame: IDentifier Extension */
		uint32_t FDF: 1; /**< LLC frame: FD frame Format */
		uint32_t BRS: 1; /**< LLC frame: Bit Rate Switching */
		uint32_t XLF: 1; /**< LLC frame: XL frame Format */
		uint32_t RMF: 1; /**< LLC frame: Remote Frame */
		uint32_t SEC: 1; /**< LLC frame: Simple or Extended Content */
		uint32_t: 2; /**< Reserved */
		uint32_t KOER: 3; /**< LLC frame: Kind Of ERror */
		uint32_t LLC_ESI: 1; /**< LLC frame: Error State Indicator */
		uint32_t LBF: 1; /**< LLC frame: Loop-Back Frame */
		uint32_t: 3; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_RBUF_FORMAT_t;

/**
 * @brief LLC frame: type structure
 */
typedef union {
	struct {
		uint32_t SDT: 8; /**< LLC frame: Service Data Type */
		uint32_t VCID: 8; /**< LLC frame: Virtual CAN ID */
		uint32_t: 16; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_RBUF_TYPE_t;

/**
 * @brief LLC frame: TTCAN cycle time structure
 */
typedef union {
	struct {
		uint32_t CYCLE_TIME: 16; /**< LLC frame: TTCAN cycle time */
		uint32_t: 16; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_RBUF_TTCAN_t;

/**
 * @brief LLC frame: IDentifier structure
 */
typedef union {
	struct {
		uint32_t ID: 29; /**< LLC frame: IDentifier */
		uint32_t: 2; /**< Reserved */
		uint32_t TTSEN: 1; /**< LLC frame: Transmit Time-stamp ENable */
	};
	uint32_t VALUE;
} CAN_CTRL_TBUF_IDENTIFIER_t;

/**
 * @brief LLC frame: format structure
 */
typedef union {
	struct {
		uint32_t DLC: 11; /**< LLC frame: Data Length Code */
		uint32_t: 5; /**< Reserved */
		uint32_t IDE: 1; /**< LLC frame: IDentifier Extension */
		uint32_t FDF: 1; /**< LLC frame: FD frame Format */
		uint32_t BRS: 1; /**< LLC frame: Bit Rate Switching */
		uint32_t XLF: 1; /**< LLC frame: XL frame Format */
		uint32_t RMF: 1; /**< LLC frame: Remote Frame */
		uint32_t SEC: 1; /**< LLC frame: Simple or Extended Content */
		uint32_t: 10; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_TBUF_FORMAT_t;

/**
 * @brief LLC frame: type structure
 */
typedef union {
	struct {
		uint32_t SDT: 8; /**< LLC frame: Service Data Type */
		uint32_t VCID: 8; /**< LLC frame: Virtual CAN ID */
		uint32_t: 8; /**< Reserved */
		uint32_t HANDLE: 8; /**< LLC frame: handle */
	};
	uint32_t VALUE;
} CAN_CTRL_TBUF_TYPE_t;

/**
 * @brief PWM Configuration structure
 */
typedef union {
	struct {
		uint32_t PWMO: 6; /**< PWM offset */
		uint32_t: 2; /**< Reserved */
		uint32_t PWMS: 6; /**< PWM Short Phase */
		uint32_t: 2; /**< Reserved */
		uint32_t PWML: 6; /**< PWM Long  Phase */
		uint32_t: 10; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_PWM_CFG_t;

/**
 * @brief Stream Interface Configuration structure
 */
typedef union {
	struct {
		uint32_t RBUFEN: 1; /**< Reception buffer enable: disabled (0) or enabled (1) */
		uint32_t RSTREN: 1; /**< Reception stream enable: disabled (0) or enabled (1) */
		uint32_t TSTREN: 1; /**< Transmission stream enable: disabled (0) or enabled (1) */
		uint32_t TSTRCFG: 2; /**< Transmission stream configuration */
		uint32_t: 27; /**< Reserved */
	};
	uint32_t VALUE;
} CAN_CTRL_STR_CFG_t;

/**
 * @brief LLC frame Size structure
 */
typedef union {
	struct {
		uint32_t LLCPBYTES: 16; /**< LLC frame Payload Bytes */
		uint32_t LLCAOT: 16; /**< LLC Address Offset of reception Time-stamps */
	};
	uint32_t VALUE;
} CAN_CTRL_LLCSIZE_t;

typedef struct {
	uint16_t VERSION; // 0x00000000: IP core version (example: 0x0515 means 5.15)
	CAN_CTRL_NODECFG_t NODECFG; // 0x00000002: CAN node configuration
	CAN_CTRL_TSCFG_t TSCFG; // 0x00000003: CiA 603 Time-Stamping Configuration
	CAN_CTRL_AC_TIME_t AC_TIME; // 0x00000004: CAN bit timing: arbitration / classic CAN
	CAN_CTRL_FD_TIME_t FD_TIME; // 0x00000008: CAN bit timing: CAN FD data bit rate
	CAN_CTRL_XL_TIME_t XL_TIME; // 0x0000000c: CAN bit timing: CAN XL data bit rate
	CAN_CTRL_PRESC_t PRESC; // 0x00000010: CAN bit timing: (all)                        prescaler
	uint8_t FD_TDC; // 0x00000011: CAN bit timing: CAN FD                       transmitter delay compensation
	uint8_t XL_TDC; // 0x00000012: CAN bit timing: CAN XL                       transmitter delay compensation
	CAN_CTRL_RELIM_t RELIM; // 0x00000013: rearbitration and retransmission limits
	CAN_CTRL_INTF_t INTF; // 0x00000014: INTerrupt Flag Register: no interrupt (0) or interrupt pending (1)
	CAN_CTRL_INTE_t INTE; // 0x00000018: INTerrupt Enable Register: disabled (0) or enabled (1)
	CAN_CTRL_TSTAT_1_t TSTAT_1; // 0x0000001c: transmit status 1
	CAN_CTRL_TSTAT_2_t TSTAT_2; // 0x0000001e: transmit status 2
	uint32_t TTS[2]; // 0x00000020: Transmission Time Stamp
	CAN_CTRL_CFG_STAT_t CFG_STAT; // 0x00000028: configuration and status
	CAN_CTRL_TCMD_t TCMD; // 0x00000029: transmit command
	CAN_CTRL_TCTRL_t TCTRL; // 0x0000002a: transmit control
	CAN_CTRL_RCTRL_t RCTRL; // 0x0000002b: receive control
	CAN_CTRL_LIMIT_t LIMIT; // 0x0000002c: warning limits
	CAN_CTRL_EALCAP_t EALCAP; // 0x0000002d: Error and Arbitration Lost CAPture
	uint8_t RECNT; // 0x0000002e: Receive  Error CouNT
	uint8_t TECNT; // 0x0000002f: Transmit Error CouNT
	CAN_CTRL_REF_MSG_t REF_MSG; // 0x00000030: TTCAN: reference message
	CAN_CTRL_TRIGCFG_0_t TRIGCFG_0; // 0x00000034: TTCAN: trigger configuration
	CAN_CTRL_TRIGCFG_1_t TRIGCFG_1; // 0x00000035: TTCAN: trigger configuration
	CAN_CTRL_TBSLOT_t TBSLOT; // 0x00000036: TTCAN: TB slot management
	CAN_CTRL_TTCFG_t TTCFG; // 0x00000037: TTCAN: configuration
	uint16_t TT_TRIG; // 0x00000038: TTCAN: trigger time
	uint16_t TT_WTRIG; // 0x0000003a: TTCAN: watch trigger time
	CAN_CTRL_FSCFG_t FSCFG; // 0x0000003c: Safety Configuration
	uint8_t reserved_0000003d[2]; // 0x0000003d: Reserved
	CAN_CTRL_MEM_STAT_t MEM_STAT; // 0x0000003f: MEMory STATus
	CAN_CTRL_MEM_ES_0_t MEM_ES_0; // 0x00000040: MEMory Error Stimulation 0
	CAN_CTRL_MEM_ES_1_t MEM_ES_1; // 0x00000041: MEMory Error Stimulation 1
	CAN_CTRL_MEM_ES_2_t MEM_ES_2; // 0x00000042: MEMory Error Stimulation 2
	CAN_CTRL_MEM_ES_3_t MEM_ES_3; // 0x00000043: MEMory Error Stimulation 3
	CAN_CTRL_ACFCTRL_t ACFCTRL; // 0x00000044: Acceptance Filter Control
	uint8_t reserved_00000045[1]; // 0x00000045: Reserved
	CAN_CTRL_ACF_EN_0_t ACF_EN_0; // 0x00000046: Acceptance filter enable, part 1
	CAN_CTRL_ACF_EN_1_t ACF_EN_1; // 0x00000047: Acceptance filter enable, part 1
	CAN_CTRL_ACFC_IDENTIFIER_t ACFC_IDENTIFIER; // 0x00000048: LLC frame: IDentifier
	CAN_CTRL_ACFC_FORMAT_t ACFC_FORMAT; // 0x0000004c: LLC frame: format
	CAN_CTRL_ACFC_TYPE_t ACFC_TYPE; // 0x00000050: LLC frame: type
	uint32_t ACFC_ACCEPTANCE_FIELD; // 0x00000054: LLC frame: Acceptance Field
	CAN_CTRL_ACFM_IDENTIFIER_t ACFM_IDENTIFIER; // 0x00000058: LLC frame: IDentifier
	CAN_CTRL_ACFM_FORMAT_t ACFM_FORMAT; // 0x0000005c: LLC frame: format
	CAN_CTRL_ACFM_TYPE_t ACFM_TYPE; // 0x00000060: LLC frame: type
	uint32_t ACFM_ACCEPTANCE_FIELD; // 0x00000064: LLC frame: Acceptance Field
	uint8_t reserved_00000068[8]; // 0x00000068: Reserved
	CAN_CTRL_RBUF_IDENTIFIER_t RBUF_IDENTIFIER; // 0x00000070: LLC frame: IDentifier
	CAN_CTRL_RBUF_FORMAT_t RBUF_FORMAT; // 0x00000074: LLC frame: format
	CAN_CTRL_RBUF_TYPE_t RBUF_TYPE; // 0x00000078: LLC frame: type
	uint32_t RBUF_ACCEPTANCE_FIELD; // 0x0000007c: LLC frame: Acceptance Field
	uint32_t RBUF_PAYLOAD[512]; // 0x00000080: LLC frame: Payload
	uint32_t RBUF_CIA_603[2]; // 0x00000880: LLC frame: CiA 603 Reception Time-stamp
	CAN_CTRL_RBUF_TTCAN_t RBUF_TTCAN; // 0x00000888: LLC frame: TTCAN cycle time
	uint8_t reserved_0000088c[4]; // 0x0000088c: Reserved
	CAN_CTRL_TBUF_IDENTIFIER_t TBUF_IDENTIFIER; // 0x00000890: LLC frame: IDentifier
	CAN_CTRL_TBUF_FORMAT_t TBUF_FORMAT; // 0x00000894: LLC frame: format
	CAN_CTRL_TBUF_TYPE_t TBUF_TYPE; // 0x00000898: LLC frame: type
	uint32_t TBUF_ACCEPTANCE_FIELD; // 0x0000089c: LLC frame: Acceptance Field
	uint32_t TBUF_PAYLOAD[512]; // 0x000008a0: LLC frame: Payload
	uint8_t reserved_000010a0[12]; // 0x000010a0: Reserved
	CAN_CTRL_PWM_CFG_t PWM_CFG; // 0x000010ac: PWM Configuration
	CAN_CTRL_STR_CFG_t STR_CFG; // 0x000010b0: Stream Interface Configuration
	uint32_t LLCFORMAT; // 0x000010b4: LLC frame Format
	CAN_CTRL_LLCSIZE_t LLCSIZE; // 0x000010b8: LLC frame Size
} CAN_CTRL_t;

#endif /* CAN_LINUX_REGISTERS_H */